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1 ltc1267 LTC1267-ADJ/ltc1267-a dj 5 dual high efficiency synchronous step-down switching regulators figure 1. high efficiency dual 3.3v, 5v s f ea t u re d u escriptio the ltc ? 1267 series are dual synchronous step-down switching regulator controllers featuring automatic burst mode tm operation to maintain high efficiencies at low output currents. the ltc1267 is composed of two sepa- rate regulator blocks, each driving a pair of external comple- mentary power mosfets at switching frequencies up to 400khz. the ltc1267 uses a constant off-time current- mode architecture to provide constant ripple current in the inductor and provide excellent line and load transient response. a separate pin and on-board switch allow the mosfet driver power to be derived from the regulated output voltage, providing significant efficiency improvement when operating at high input voltage. the output current level is user-programmable via an external current sense resistor. the ltc1267 series is ideal for applications requiring dual output voltages with high conversion efficiencies over a wide load current range in a small amount of board space. n dual outputs: 3.3v and 5v, two adjustables or adjustable and 5v n wide v in range: 4v to 40v n ultra-high efficiency: up to 95% n low supply current in shutdown: 20 m a n current mode operation for excellent line and load transient response n high efficiency maintained over a wide output current range n independent micropower shutdown n very low dropout operation: 100% duty cycle n synchronous fet switching for high efficiency n available in standard 28-pin ssop n notebook and palmtop computers n battery-operated digital devices n portable instruments n dc power distribution systems u s a o pp l ic at i , ltc and lt are registered trademarks of linear technology corporation. burst mode is a trademark of linear technology corporation. u a o pp l ic at i ty p i ca l 1000pf + + + 1000pf pgate 3 pdrive 3 sense + 3 sense ? 3 sense ? 5 shdn3 pdrive 5 shdn5 ngate 3 pgnd3 sgnd3 c t3 i th3 i th5 c t5 sgnd5 pgnd5 ngate 5 sense + 5 pgate 5 v cc3 v cc v in cap3 cap5 mshdn v cc5 ext v cc ltc1267 c t5 270pf 7 11 9 10 15 16 20 22 r c5 1k c c3 3300pf c c5 3300pf c t3 270pf r c3 1k 1 3 0.15 m f 0.15 m f 8 1n4148 26 27 221 28 25 24 18 17 19 23 4 5 14 13 12 6 v out5 5v 2a c out5 220 m f 10v 2 r sense5 0.05 w p-ch si9435dy l5 33 m h d5 mbrs140t3 n-ch si9410dy c in5 100 m f 50v + 3.3 m f 0.1 m f 0.1 m f c in3 100 m f 50v p-ch si9435dy n-ch si9410dy d3 mbrs140t3 c out3 220 m f 10v 2 l3 20 m h r sense3 0.05 w v out3 3.3v 2a v in 5.4v to 25v r sense3 : krl sl-1r050j l3: coiltronics ctx20-4 r sense5 : krl sl-1r050j l5: coiltronics ctx33-4 shdn3, shdn5, mshdn 0v = normal, >2v = shdn ltc1267 ?f01 + 3.3 m f + 1n4148
2 ltc1267 LTC1267-ADJ/LTC1267-ADJ 5 a u g w a w u w a r b s o lu t exi t i s input supply voltage (pin 2)..................... C 0.3v to 40v v cc output current (pin 1) .................................. 50ma ext v cc input voltage (pin 28) .............................. 10v continuous output current (pins 5, 6, 23, 24) .... 50ma sense voltages ltc1267 (pins 13, 14, 17, 18) ............. v cc to C 0.3v LTC1267-ADJ (pins 12, 13, 17, 18) ..... v cc to C 0.3v LTC1267-ADJ5 (pins 12, 13, 17, 18) ... v cc to C 0.3v shutdown voltages ltc1267 (pins 12, 19, 27) ................................... 7v LTC1267-ADJ (pins 11, 27) ................................. 7v LTC1267-ADJ5 (pins 11, 19, 27) ......................... 7v operating ambient temperature range ...... 0 c to 70 c extended commercial temperature range ........................... C 40 c to 85 c junction temperature (note 1) ............................ 125 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c wu u package / o rder i for atio order part number ltc1267cg order part number ltc1267cg-adj5 order part number ltc1267cg-adj consult factory for industrial and military grade parts. the ltc1267 demo circuit board is now available. consult factory. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v cc v in cap3 pgate 3 pdrive 3 ngate 3 pgnd3 v cc3 c t3 i th3 sgnd3 shdn3 sense 3 sense + 3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 g package 28-lead plastic ssop t jmax = 125 c, q ja = 95 c/w top view ext v cc mshdn cap5 pgate 5 pdrive 5 ngate 5 pgnd5 v cc5 sgnd5 shdn5 sense + 5 sense 5 c t5 i th5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v cc v in cap1 pgate 1 pdrive 1 ngate 1 v cc1 c t1 i th1 sgnd1 shdn1 sense 1 sense + 1 v fb1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 g package 28-lead plastic ssop t jmax = 125 c, q ja = 95 c/w top view ext v cc mshdn cap5 pgate 5 pdrive 5 ngate 5 pgnd v cc5 sgnd5 shdn5 sense + 5 sense 5 c t5 i th5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v cc v in cap1 pgate 1 pdrive 1 ngate 1 v cc1 c t1 i th1 sgnd1 shdn1 sense 1 sense + 1 v fb1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 g package 28-lead plastic ssop t jmax = 125 c, q ja = 95 c/w top view ext v cc mshdn cap2 pgate 2 pdrive 2 ngate 2 pgnd v cc2 sgnd2 v fb2 sense + 2 sense 2 c t2 i th2
3 ltc1267 LTC1267-ADJ/ltc1267-a dj 5 e lectr ic al c c hara terist ics t a = 25 c, v in = 12v, v mshdn, v shdn1,3,5 = 0v (note 2), unless otherwise noted. symbol parameter conditions min typ max units v fb1 , 2 feedback voltage LTC1267-ADJ, LTC1267-ADJ5: v in = 9v l 1.21 1.25 1.29 v i fb1 , 2 feedback current LTC1267-ADJ, LTC1267-ADJ5 l 0.2 1 m a v out regulated output voltage 3.3v output ltc1267: v in = 9v, i load = 700ma l 3.23 3.33 3.43 v 5v output ltc1267, LTC1267-ADJ5: v in = 9v, i load = 700ma l 4.90 5.05 5.20 v d v out output voltage line regulation v in = 9v to 40v C 40 0 40 mv output voltage load regulation figure 1 circuit 3.3v output 5ma < i load < 2.0a l 40 65 mv 5v output 5ma < i load < 2.0a l 60 100 mv burst mode output ripple i load = 0a 50 mv p-p v cc internal regulator voltage v in = 12v to 40v, ext v cc = 0v, i cc = 10ma l 4.25 4.5 4.75 v v in C v cc v cc dropout voltage v in = 4v, ext v cc = open, i cc = 10ma 200 300 mv i extvcc ext v cc pin current (note 3) ext v cc = 5v, sleep mode 360 m a i in v in pin current (note 3) normal v in = 12v, ext v cc = 5v 320 m a v in = 40v, ext v cc = 5v 550 m a shutdown v in = 12v, v mshdn = 2v 15 m a v in = 40v, v mshdn = 2v 25 m a v extvcc C ext v cc switch drop v in = 12v, ext v cc = 5v, i switch = 10ma 200 300 mv v cc v pgate C pgate to source voltage (off) v in = 12v C 0.2 0 v v in v in = 40v C 0.2 0 v v sense + 1, 2 C current sense threshold voltage LTC1267-ADJ, LTC1267-ADJ5 v sense C 1, 2 v sense C 1, 2 = 5.1v, v fb1, 2 = v out /4 + 25mv (forced) 25 mv v sense C 1, 2 = 4.9v, v fb1, 2 = v out /4 C 25mv (forced) l 135 160 180 mv v sense + 3, 5 C current sense threshold voltage ltc1267 v sense C 3, 5 v sense C 3, 5 = v out + 100mv (forced) 25 mv v sense C 3, 5 = v out C 100mv (forced) l 135 160 180 mv v shdn shutdown threshold mshdn 0.8 1.4 2.0 v shdn1, 3, 5 0.6 0.8 2.0 v i mshdn mshdn input current v mshdn = 5v 12 20 m a i ct c t pin discharge current v out in regulation 50 70 90 m a v out = 0v 2 10 m a t off off-time (note 4) c t = 390pf, i load = 700ma, v in = 10v 4 5 6 m s t r , t f driver output transition times c l = 3000pf (pdrive and ngate pins), v in = 6v 100 200 ns
4 ltc1267 LTC1267-ADJ/LTC1267-ADJ 5 symbol parameter conditions min typ max units v fb1 , 2 feedback voltage LTC1267-ADJ, LTC1267-ADJ5: v in = 9v 1.2 1.25 1.3 v v out regulated output voltage v in = 9v 3.3v output i load = 700ma 3.17 3.30 3.48 v 5v output i load = 700ma 4.85 5.05 5.25 v i in v in pin current (note 3) normal v in = 12v, ext v cc = 5v 320 m a v in = 40v, ext v cc = 5v 550 m a shutdown v in = 12v, v mshdn = 2v 15 m a v in = 40v, v mshdn = 2v 25 m a i extvcc ext v cc pin current (note 3) ext v cc = 5v, sleep mode 360 m a v cc internal regulator voltage v in = 12v to 40v, ext v cc = 0v, i cc = 20ma 4.5 v v sense + C current sense threshold voltage low threshold (forced) 25 mv v sense C high threshold (forced) 130 160 185 mv v mshdn shutdown threshold mshdn 0.8 1.4 2.0 v t off off-time (note 4) c t = 390pf, i load = 700ma, v in = 10v 3 5 7 m s e lectr ic al c c hara terist ics C40 c t a 85 c, v in = 12v, v mshdn, v shdn1,3,5 = 0v (notes 2, 5), unless otherwise noted. the l denotes specifications which apply over the full operating temperature range. note 1: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: ltc1267/LTC1267-ADJ/ltc1267adj5: t j = t a + (p d 95 c/w) note 2: on ltc1267 versions which have mshdn and shdn1, 3, 5 pins, they must be at ground potential for testing. note 3: the ltc1267 v in and ext v cc current measurements exclude mosfet driver currents. when v cc power is derived from the output via ext v cc , the input current increases by (i gatechg duty cycle)/efficiency. see typical performance characteristics and applications information. note 4: in applications where r sense is placed at ground potential, the off-time increases approximately 40%. note 5: the ltc1267/LTC1267-ADJ/LTC1267-ADJ5 are not tested and quality-assurance sampled at C 40 c to 85 c. these specifications are guaranteed by design and/or correlation. note 6: the logic level power mosfets shown in figure 1 are rated for v ds(max) = 30v. for operation at v in > 30v, use standard threshold mosfets with ext v cc powered from a 9v supply. see applications information. note 7: LTC1267-ADJ and LTC1267-ADJ5 are tested at an output of 3.3v typical perfor m a n ce characteristics u w load current (a) 0.01 80 efficiency (%) 90 100 0.1 1 10 ltc1267 ?g01 70 75 85 95 65 60 v in = 10v v in = 20v 5v output efficiency vs load current load current 0 ?0 d output voltage (mv) ?0 ?0 ?0 ?0 1.0 2.0 2.5 30 ltc1267 ?g03 ?0 0.5 1.5 0 10 20 v in = 10v v out = 3.3v v in = 20v v out = 3.3v v in = 10v v out = 5v v in = 20v v out = 5v load regulation load current (a) 0.01 80 efficiency (%) 90 100 0.1 1 10 ltc1267 ?g02 70 75 85 95 65 60 v in = 10v v in = 20v 3.3v output efficiency vs load current
5 ltc1267 LTC1267-ADJ/ltc1267-a dj 5 typical perfor m a n ce characteristics u w 5v output efficiency vs line voltage line regulation 3.3v output efficiency vs line voltage input voltage (v) 0 efficiency (%) 80 85 90 40 ltc1267 ?g04 75 70 60 10 20 30 65 100 95 5 15 25 35 logic threshold gate, 1a standard threshold gate, 1a v extvcc = 9v logic threshold gate, 0.1a standard threshold gate, 0.1a v extvcc = 9v note 6 input voltage (v) 0 efficiency (%) 80 85 90 40 ltc1267 ?g05 75 70 60 10 20 30 65 100 95 5 15 25 35 logic threshold gate, 1a standard threshold gate, 1a v extvcc = 9v logic threshold gate, 0.1a standard threshold gate, 0.1a v extvcc = 9v note 6 input voltage (v) 0 ?0 d output voltage (mv) ?0 ?0 0 20 10 20 30 40 lt1267 ?g06 40 60 515 25 35 note 6 operating frequency vs (v in C v out ) current sense threshold voltage (v in ?v out ) voltage (v) 0 normalized frequency (hz) 1.0 1.5 20 ltc1267 ?g07 0.5 0 5 10 15 25 2.0 0 c 25 c v out = 5v i load = 700ma 70 c off-time vs output voltage output voltage (v) 0 off-time ( m s) 120 160 4.0 ltc1267 ?f08 80 40 100 140 60 20 0 1.0 2.0 3.0 0.5 4.5 1.5 2.5 3.5 5.0 3.3v output regulator 5v output regulator temperature ( c) 0 0 sense voltage (mv) 20 60 80 100 20 180 ltc1267 ?g09 40 10 30 40 50 60 70 80 90 100 120 140 160 minimum threshold maximum threshold pi fu ctio s u uu (applies to both regulator sections) v in : main supply input pin. ext v cc : external v cc supply for the regulators. see ext v cc pin connection. v cc : output of the internal 4.5v linear regulator, ext v cc switch, and supply inputs for driver and control circuits. the driver and control circuits are powered from the higher of the 4.5v regulator or ext v cc voltage. must be closely decoupled to the power ground. pgnd: power ground. connect to the source of n-channel mosfet and the (C) terminal of c in . sgnd: small-signal ground. must be routed separately from other grounds to the (C) terminal of c out . pgate: level shifted gate drive for the top p-channel mosfet. the voltage swing at the pgate pin is from v in to (v in C v cc ). pdrive: high current gate drive for the top p-channel mosfet. the pdrive pin swings from v cc to gnd. ngate: high current drive for the bottom n-channel mosfet. the ngate pin swings from gnd to v cc .
6 ltc1267 LTC1267-ADJ/LTC1267-ADJ 5 pi fu ctio s u uu cap: charge compensation pin. a capacitor to v cc pro- vides charge required by the pgate level shift capacitor during supply transitions. the charge compensation ca- pacitor must be larger than the gate drive capacitor. c t : external capacitor. from this pin to ground sets the operating frequency. (the frequency is also dependent upon the ratio v out /v in ). i th : gain amplifier decoupling point. the regulator cur- rent comparator threshold increases with the i th pin voltage. sense C : connects to internal resistive divider which sets the output voltage. the sense C pin is also the (C) input of the current comparator. sense + : the (+) input for the current comparator. a built-in offset between the sense + and sense C pins, in conjunction with r sense , sets the current trip threshold. v fb1, 2 : these pins receive the feedback voltage from an external resistive divider used to set the output voltage of the adjustable section. mshdn: master shutdown pin. taking mshdn high shuts down v cc and all control circuitry. shdn1, 3, 5: these pins shut down the individual regula- tor control circuitry (v cc is not affected). taking shdn1, 3, 5 pins high turns off the control circuitry of adjustable 1, 3.3v, 5v sections and holds both mosfets off. must be at ground potential for normal operation. fu ctio al diagra u uw (internal divider broken at v fb1,2 for adjustable versions. only one regulator block shown.) r s q + c 25mv to 150mv 13k i th 1.25v reference + sgnd shdn1, 3, 5 v os + v g sense + v fb1, 2 100k + v th1 t + v th2 s sleep c t pgnd v cc v in ext v cc mshdn ngate pdrive pgate off-time control sense sense ltc1267 ?fd cap v cc 550k low dropout switch low dropout 4.5v regulator 550k
7 ltc1267 LTC1267-ADJ/ltc1267-a dj 5 operatio u (refer to functional diagram) the ltc1267 series consists of two individual regulator blocks, each using current mode, constant off-time archi- tectures to synchronously switch an external pair of complementary power mosfets. the two regulators are internally set to provide output voltages of 3.3v and 5v for the ltc1267. the LTC1267-ADJ is configured to provide two adjustable output voltages, each set by their indi- vidual external resistor dividers. the LTC1267-ADJ5 has adjustable and 5v output voltages. operating frequency is individually set on each section by the external capacitors attached to the c t pin. the output voltage is sensed by an internal voltage divider connected to the sense C pin or external divider returned to the v fb pin (LTC1267-ADJ, LTC1267-ADJ5). a voltage comparator v and a gain block g compare the divided output voltage with a reference voltage of 1.25v. to optimize efficiency, the ltc1267 series automatically switches between two modes of operation, burst mode and continuous mode. the voltage comparator is the primary control element when the device is in burst mode operation, while the gain block controls the output voltage in continuous mode. a low dropout 4.5v regulator provides the operating voltage v cc for the mosfet drivers and control circuitry during start-up. during normal operation, the ltc1267 family powers the drivers and control from the output via the ext v cc pin to improve efficency. the ngate pin is referenced to ground and drives the n-channel mosfet gate directly. the p-channel gate drive must be referenced to the main supply input v in , which is accomplished by level-shifting the pdrive signal via an internal 550k resis- tor and an external capacitor. during the switch on cycle in continuous mode, current comparator c monitors the voltage between sense + and sense C pins connected across an external shunt in series with the inductor. when the voltage across the shunt reaches its threshold value, the pgate output is switched to v in , turning off the p-channel mosfet. the timing capacitor c t is now allowed to discharge at a rate deter- mined by the off-time controller. the discharge current is made proportional to the output voltage to model the inductor current, which decays at a rate that is also proportional to the output voltage. while the timing ca- pacitor is discharging, the ngate output is high, turning on the n-channel mosfet. when the voltage on the timing capacitor has discharged past v th1 , comparator t trips, setting the flip-flop. this causes the ngate output to go low (turning off the n-channel mosfet) and the pgate output to also go low (turning the p-channel mosfet back on). the cycle then repeats. as the load current increases, the output voltage decreases slightly. this causes the output of the gain stage to increase the current comparator threshold, thus tracking the load current. the sequence of events for burst mode operation is very similar to continuous operation with the cycle interrupted by the voltage comparator. when the output voltage is at or above the desired regulated value, the p-channel mosfet is held off by comparator v and the timing capacitor continues to discharge below v th1 . when the timing capacitor discharges past v th2 , voltage compara- tor s trips, causing the internal sleep line to go low and the n-channel mosfet to turn off. the circuit now enters sleep mode with both power mosfets turned off. in sleep mode a majority of the circuitry is turned off, dropping the quiescent current from several ma (with the mosfets switching) to 360 m a. the load current is now being supplied by the output capacitor. when the output voltage has dropped by the amount of hysteresis in comparator v, the p-channel mosfet is again turned on and this process repeats. to avoid the operation of the current loop interfering with burst mode operation, a built-in offset v os is incorporated in the gain stage. this prevents the current comparator threshold from increasing until the output voltage has dropped below a minimum threshold. to prevent both the external mosfets from ever being turned on at the same time, feedback is incorporated to sense the state of the driver output pins. before the ngate output can go high, the pdrive output must also be high. likewise, the pdrive output is prevented from going low while the ngate output is high.
8 ltc1267 LTC1267-ADJ/LTC1267-ADJ 5 the ltc1267 compared to the ltc1159, ltc1149 and ltc1142 family the ltc1267 family is a dual ltc1159. identical to the ltc1159, the ltc1267 can reduce the quiescent and shutdown currents by making use of an internal switch which allows the driver and control sections to be powered from an external source to improve efficiency. the basic ltc1267 application circuit shown in figure 1 is limited to a maximum input voltage of 30v due to external mosfet breakdown. if the application does not require greater than 18v operation the ltc1142hv should be used. component selection t he basic ltc1267 application circuit is shown in figure 1. external component selection is driven by the load requirement and begins with the selection of r sense . once r sense is known, c t and l can be chosen. next, the power mosfets and diode are selected. finally, c in and c out are selected and the loop is compensated. since the adjustable, 3.3v and 5v sections in the ltc1267 are identical, the process of component selection is the same for both sections. r sense selection for output current r sense is chosen based on the required output current. the ltc1267 current comparators have a threshold range which extends from a minimum of 25mv/r sense to a maximum of 150mv/r sense . the current comparator threshold sets the peak of the inductor ripple current, yielding a maximum output current i max equal to the peak value less half the peak-to-peak ripple current. for proper burst mode operation, i ripple(p-p) must be less than or equal to the minimum current comparator threshold. since efficiency generally increases with ripple current, the maximum allowable ripple current is assumed, i.e., i ripple(p-p) = 25mv/r sense (see c t and l selection for operating frequency). solving for r sense and allowing a margin for variations in the ltc1267 and external compo- nent values yields: r sense = 100mv i max applicatio s i for atio w uu u the ltc1267 works well with values of r sense from 0.02 w to 0.2 w . figure 2 shows the selection of r sense vs maximum output current. maximum output current (a) 0 r sense ( w ) 0.20 0.15 0.10 0.05 0 4 ltc1267 ?f02 1 2 3 5 figure 2. selecting r sense the load current below which burst mode operation com- mences, i burst and the peak short-circuit current i sc(pk) both track i max . once r sense has been chosen, i burst and i sc(pk) can be predicted from the following: i burst ? 15mv r sense i sc(pk) = 150mv r sense the ltc1267 automatically extends t off during a short circuit to allow sufficient time for the inductor current to decay between switch cycles. the resulting ripple current causes the average short-circuit current i sc(avg) to be reduced to approximately i max . c t and l selection for operating frequency each regulator section of the ltc1267 uses a constant off- time architecture with t off determined by an external timing capacitor c t . the value of c t is calculated from the desired continuous mode operating frequency (f o ): c t = 1 7.8 10 ? f o v out v in ) ) a graph for selecting c t vs frequency including the effects of input voltage is given in figure 3.
9 ltc1267 LTC1267-ADJ/ltc1267-a dj 5 applicatio s i for atio w uu u value, but it is very dependent on inductance selected. as inductance increases, core losses go down but copper i 2 r losses increase. for additional information regarding in- ductor selection, please refer to the ltc1159 data sheet. power mosfet and diode selection two external power mosfets must be selected for use with each section of the ltc1267: a p-channel mosfet for the main switch, and an n-channel mosfet for the synchronous switch. the peak-to-peak gate drive levels are set by the v cc voltage on the ltc1267. this voltage is typically 4.5v during start-up and 5v to 7v during normal operation (see ext v cc pin connection). consequently, logic-level thresh- old mosfets must be used in most ltc1267 family applications . the only exceptions are applications in which ext v cc is powered from an external supply greater than 8v, in which standard threshold mosfets (v gs(th) > 4v) may be used. pay close attention to the bv dss specification for the mosfets as well; many of the logic- level mosfets are limited to 30v. selection criteria for the power mosfets include the on- resistance r ds(on) , reverse transfer capacitance c rss , input voltage, and maximum output current. when the ltc1267 is operating in continuous mode, the duty cycles for the two mosfets are given by: duty cycle = v out v in n-channel duty cycle = v in ?v out v in the mosfet dissipations at maximum output current are given by: p-ch p d =(i max ) 2 (1 + d p ) r ds(on) + k (v in ) 2 (i max ) (c rss ) f o v out v in n-ch p d =(i max ) 2 (1 + d n ) r ds(on) v in ?v out v in frequency (khz) 0 1000 1200 1400 150 200 ltc1267 ?f03 800 600 50 100 250 400 200 0 timing capacitance (pf) v out = 5v v in = 24v v in = 12v figure 3. timing capacitor value as the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see efficiency considerations). the complete expression for operating frequency is given by: f o = 1 t off ) ) 1 v out v in where: t off = 1.3 10 4 c t once the frequency has been set by c t , the inductor l must be chosen to provide no more than 0.025v/r sense of peak-to-peak inductor ripple current. this results in a minimum required inductor value of: l min = 5.1 10 5 r sense c t v out as the inductor value is increased from the minimum value, the esr requirements for the output capacitor are eased at the expense of efficiency. if too small an inductor is used, the ltc1267 may not enter burst mode operation and efficiency will be severely degraded at low currents. inductor core selection once the minimum value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy (mpp), or kool m m ? cores. actual core loss is independent of core size for a fixed inductor kool m m is a registered trademark of magnetics, inc.
10 ltc1267 LTC1267-ADJ/LTC1267-ADJ 5 applicatio s i for atio w uu u where d is the temperature dependency of r ds(on) and k is a constant inversely related to the gate drive current. both mosfets have i 2 r losses, while the p-channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v, the high current efficiency generally improves with larger mosfets, while for v in > 20v, the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c rss actually provides higher efficiency. the n-channel mosfet losses are the greatest at high input voltage or during a short circuit when the n-channel duty cycle is nearly 100%. the term (1 + d ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.007/ c can be used as an approximation for low voltage mosfets. c rss is usually specified in the mosfet electrical characteristics. the constant k = 5 can be used for the ltc1267 to estimate the relative contributions of the two terms in the p-channel dissipation equation. the schottky diodes d3 and d5 shown in figure 1 only conduct during the dead-time between the conduction of the respective power mosfets. the sole purpose of d3 and d5 is to prevent the body diode of the n-channel mosfet from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency (although there are no other harmful effects if d3 and d5 are omitted). therefore, d3 and d5 should be selected for a forward voltage of less than 0.6v when conducting i max . c in and c out selection in continuous mode, the source current of the p-channel mosfet is a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr input capaci- tor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: c in required i rms ? i max [v out (v in v out )] 1/2 v in this formula has a maximum at v in = 2v out where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. an additional 0.1 m f ceramic capacitor is also required on v in for high frequency decoupling. the selection of c out is driven by the required effective series resistance (esr). the esr of c out must be less than twice the value of r sense for proper operation of the ltc1267: c out required esr < 2r sense optimum efficiency is obtained by making the esr equal to r sense . as the esr is increased up to 2r sense , the efficiency degrades by less than 1%. if the esr is greater than 2r sense , the voltage ripple on the output capacitor will prematurely trigger burst mode operation, resulting in disruption of continuous mode and an efficiency hit which can be several percent. manufacturers such as nichicon, united chemicon, and sprague should be considered for high performance ca- pacitors. in surface mount applications multiple capaci- tors may have to be paralleled to meet the capacitance, esr, or rms current handling requirements of the appli- cation. for additional information regarding capacitor selection, please refer to the ltc1159 data sheet. at low supply voltages, a minimum capacitance at c out is needed to prevent an abnormal low frequency operating mode (see figure 4). when c out is made too small, the output ripple at low frequencies will be large enough to trip figure 4. minimum suggested c out (v in ?v out ) voltage (v) 0 output capacitance ( m f) 1000 800 600 400 200 0 4 ltc1267 ?f04 1 2 3 5 l = 50 m h r sense = 0.02 w l = 25 m h r sense = 0.02 w l = 50 m h r sense = 0.05 w
11 ltc1267 LTC1267-ADJ/ltc1267-a dj 5 applicatio s i for atio w uu u the voltage comparator. this causes burst mode opera- tion to be activated when the ltc1267 would normally be in continuous operation. the effect is most pronounced with low values of r sense and can be improved by oper- ating at higher frequencies with lower values of l. the output remains in regulation at all times. ext v cc pin connection the ltc1267 contains an internal pnp switch connected between the ext v cc and v cc pins. the switch closes and supplies the v cc power whenever the ext v cc pin is higher in voltage than the 4.5v internal regulator. this allows the mosfet driver and control power to be derived from the output during normal operation and from the internal regulator when the output is out of regulation (start-up, short circuit). significant efficiency gain can be realized by powering v cc from the output, since the v in current resulting from the driver and control currents will be scaled by a factor of duty cycle/efficiency. for ltc1267, LTC1267-ADJ or LTC1267-ADJ5 this simply means connecting the ext v cc pin directly to v out of the 5v regulator. the following list summarizes the four possible connec- tions for ext v cc : 1. ext v cc left open. this will cause v cc to be powered only from the internal 4.5v regulator, resulting in re- duced mosfet gate drive levels and an efficiency penalty of up to 10% at high input voltages. 2. ext v cc connected directly to highest v out of the two regulators. this is the normal connection for ltc1267/ LTC1267-ADJ/LTC1267-ADJ5 and provides the high- est efficiency. 3. ext v cc connected to an output-derived boost net- work. for 3.3v and other low voltage regulators, effi- ciency gains can still be realized by connecting ext v cc to an output-derived voltage which has been boosted to greater than 4.5v. this can be done either with the inductive boost winding shown in figure 5a or the capacitive charge pump shown in figure 5b. the charge pump has the advantage of simple magnetics and generally provides the highest efficiency at the expense of a slightly higher parts count. + v in v in c in l 1:1 r sense 1n4148 + c out v out 3.3v + 1 m f p-ch ltc1267 ?f05a n-ch ext v cc pgate 3 pdrive 3 ltc1267 ngate 3 pgnd3 figure 5a. inductive boost circuit for ext v cc + v in v in c in r sense l + c out v out 3.3v bat 85 vn2222ll bat 85 bat 85 0.22 m f 1 m f p-ch ltc1267 ?f05b n-ch ext v cc pgate 3 pdrive 3 ltc1267 ngate 3 pgnd3 + figure 5b. capacitive charge pump for ext v cc 4. ext v cc connected to an external supply. if an external supply is available in the 5v to 10v range it may be used to power ext v cc providing it is compatible with the mosfet gate drive requirements. when driving stan- dard threshold mosfets, the external supply must always be present during operation to prevent mosfet failure due to insufficient gate drive. under the condition that ext v cc is connected to v out1 which is greater than 5.5v, to power down the whole regulator, both the pins mshdn and shdn1 have to be pulled high. if shdn1 is left floating or grounded the ext v cc may self-power from v out1 , preventing com- plete shutdown. ltc1267 adjustable applications when an output voltage other than 3.3v or 5v is required, the LTC1267-ADJ and LTC1267-ADJ5 adjustable ver- sions are used with an external resistive divider from v out to the v fb1, 2 pins. this is shown in figure 6. the regulated voltage is determined by: v out = 1.25v ) ) 1 + r2 r1
12 ltc1267 LTC1267-ADJ/LTC1267-ADJ 5 applicatio s i for atio w uu u 1. ltc1267 v in current is the dc supply current given in the electrical characteristics which excludes mosfet driver and control currents. v in currents results in a small (<1%) loss which increases with v in . 2. ltc1267 v cc current is the sum of the mosfet driver and control circuits currents. the mosfet driver cur- rent results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from v cc to ground. the resulting dq/dt is a current out of v cc which is typically much larger than the control circuit current. in continuous mode i gatechg ? f o (q p +q n ), where q p and q n are the gate charges of the two mosfets. by powering ext v cc from an output-derived source, the additional v in current resulting from the driver and control currents will be scaled by a factor of duty cycle/ efficiency. for example, in a 20v to 5v application, 10ma of v cc current results in approximately 3ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are easily predicted from the dc resistances of the mosfet, inductor, and current shunt. in continu- ous mode all the output current flows through l and r sense , but is chopped between the p-channel and n- channel mosfets. if the two mosfets have approxi- mately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and r sense to obtain i 2 r losses. for example, if each r ds(on) = 0.1 w , r l = 0.15 w , and r sense = 0.05 w , then the total resistance is 0.3 w . this results in losses ranging from 3% to 12% as the output current increases from 0.5a to 2a. i 2 r losses cause the efficiency to roll off at high output currents. 4. transition losses apply only to the p-channel mosfet and only when operating at high input voltages (typically 20v or greater). transition losses can be estimated from: transition loss ? 5 v in 2 i max c rss f o other losses including c in and c out esr dissipative losses, schottky conduction losses during dead-time, the v fb1, 2 pin is extremely sensitive to pickup from the inductor switching node. care should be taken to isolate the feedback network from the inductor and a 100pf capacitor should be connected between the v fb1, 2 and sgnd pins next to the package. the circuit in figure 6 cannot be used to regulate a v out which is greater than the maximum voltage allowed on the ltc1267 ext v cc pin (10v). in applications with v out > 10v, r sense must be moved to the ground side of the output capacitor and load. this operates the current sense comparator at 0v common mode, increasing the off-time approximately 40% and requiring the use of a smaller timing capacitor c t . efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: % efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc., are the individual losses as a percent- age of input power. (for high efficiency circuits, only small errors are incurred by expressing losses as a percentage of output power.) although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc1267 circuits: 1. ltc1267 v in current 2. ltc1267 v cc current 3. i 2 r losses 4. p-channel transition losses figure 6. LTC1267-ADJ/LTC1267-ADJ5 external feedback network r sense 100pf r2 r1 + c out v out v fb1, 2 sgnd ltc1267 ?f06
13 ltc1267 LTC1267-ADJ/ltc1267-a dj 5 applicatio s i for atio w uu u and inductor core losses, generally account for less than 2% total additional loss. auxiliary windingsCCsuppressing burst mode operation the ltc1267 synchronous switch removes the normal limitation that power must be drawn from the inductor primary winding in order to extract power from auxiliary windings. with synchronous switching, auxiliary outputs may be loaded without regard to the primary output load, providing that the loop remains in continuous mode operation. burst mode operation can be suppressed at low output currents with a simple external network which cancels the 25mv minimum current comparator threshold. this tech- nique is also useful for eliminating audible noise from certain types of inductors in high current (i out > 5a) applications when they are lightly loaded. an external offset is put in series with the sense C pin to subtract from the built-in 25mv offset. an example of this technique is shown in figure 7. two 100 w resistors are inserted in series with the sense leads from the sense resistor. l r sense + c out ltc1267 ?f07 sense + ltc1267 1000pf r3 sense r2 100 w r1 100 w figure 7. suppressing burst mode operation with the addition of r3 a current is generated through r1 causing an offset of: v offset = v out ) ) r1 r1 + r3 if v offset > 25mv, the built-in offset will be cancelled and burst mode operation is prevented from occurring. since v offset is constant, the maximum load current is also decreased by the same offset. thus, to get back to the same i max , the value of the sense resistor must be reduced: r sense ? m w 75 i max to prevent noise spikes from erroneously tripping the current comparator, a 1000pf capacitor is needed across sense + and sense C pins. board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc1267. these items are also illustrated graphically in the layout diagram of figure 8. in general each block should be self-contained with little cross coupling for best performance. check the following in your layout: 1. are the signal and power grounds segregated? the ltc1267 signal ground must return to the (C) plate of c out . the power ground returns to the source of the n-channel mosfet, anode of the schottky diode, and (C) plate of c in , which should have as short lead lengths as possible. 2. does the ltc1267 sense C pin connect to a point close to r sense and the (+) plate of c out ? in adjustable applications the resistive divider r1 and r2 must be connected between the (+) plate of c out and signal ground. 3. are the sense C and sense + leads routed together with minimum pc trace spacing? the 1000pf capacitor between the two sense pins should be as close as possible to the ltc1267. up to 100 w may be placed in series with each sense lead to help decouple the sense pins. however, when these resistors are used the capacitor should be no larger than 1000pf. 4. does the (+) plate of c in connect to the source of the p-channel mosfet as closely as possible? an addi- tional 0.1 m f ceramic capacitor between v in and power ground may be required in some applications. 5. is the v cc decoupling capacitor connected closely between the v cc pins of the ltc1267 and power ground? this capacitor carries the mosfet driver peak currents.
14 ltc1267 LTC1267-ADJ/LTC1267-ADJ 5 applicatio s i for atio w uu u figure 8. ltc1267 layout diagram 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ltc1267 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v in cap3 pgate 3 pdrive 3 ngate 3 pgnd3 c t3 i thr3 sgnd3 shdn3 sense 3 sense + 3 ext v cc mshdn cap5 pgate 5 pdrive 5 ngate 5 pgnd5 sgnd5 shdn5 sense + 5 sense 5 c t5 i thr5 v cc 0.15 m f v cc3 c in3 c in5 c out5 v out5 v in c t3 v cc5 + + + 0.15 m f 0.1 m f mshdn shdn5 1n4148 bold lines indicate high current paths 1n4148 p-ch p-ch 3300pf 1k n-ch n-ch d3 l3 0.1 m f 1 m f 1 m f c t5 1000pf 3300pf 1k ltc1267 ?f08 r sense3 r sense5 v out3 c out3 d5 + + + 1000pf l5 shdn3 6. in adjustable versions, the feedback pin is very sensi- tive to pickup from the switch node. care must be taken to isolate v fb1, 2 from possible capacitive coupling of the inductor switch signal. 7. are mshdn and shdn1, 3, 5 actively pulled to ground during normal operation? these shutdown pins are high impedance and must not be allowed to float. troubleshooting hints since efficiency is critical to ltc1267 applications, it is very important to verify that the circuit is functioning correctly in both continuous and burst mode operation. the waveform to monitor is the voltage on the c t pin. in continuous mode (i load > i burst ) the voltage on the c t pin should be a sawtooth with a 0.9v p-p swing. this voltage should never dip below 2v as shown in figure 9a. when load currents are low (i load < i burst ) burst mode operation occurs. the voltage on the c t pin now falls to ground for periods of time as shown in figure 9b. if the c t is observed falling to ground at high output currents, it indicates poor decoupling or improper ground- ing. refer to the board layout checklist. inductor current should also be monitored. look to verify that the peak-to-peak ripple current in continuous mode operation is approximately the same as in burst mode operation. 3.3v 0v (a) continuous mode operation 3.3v 0v (b) burst mode operation ltc1267 ?f09 figure 9. c t waveforms
15 ltc1267 LTC1267-ADJ/ltc1267-a dj 5 1000pf + + + 1000pf pgate 1 pdrive 1 sense + 1 sense ? 1 sense ? 2 shdn1 pdrive 2 ngate 1 v fb1 v fb2 sgnd1 c t1 i th1 i th2 c t2 sgnd2 ngate 2 sense + 2 pgate 2 pgnd2 v cc1 v cc v in cap1 cap2 mshdn v cc2 ext v cc LTC1267-ADJ c t2 270pf 14 100pf 10 8 9 15 16 20 19 r c2 1k c c1 3300pf c c2 3300pf c t1 270pf r c1 1k 1 3 0.15 m f 0.15 m f 726 27 221 1n4148 28 25 24 18 17 22 23 4 5 13 12 11 6 v out2 5v 2a c out2 220 m f 10v 2 r sense2 0.05 w p-ch si9435dy l2 33 m h d2 mbrs140t3 n-ch si9410dy c in2 100 m f 50v + 3.3 m f 0.1 m f 0.1 m f c in1 100 m f 50v p-ch si9435dy n-ch si9410dy d1 mbrs140t3 c out1 220 m f 10v 2 l1 20 m h r sense1 0.04 w v out1 3.6v 2.5a v in 5.4v to 25v r sense1 : krl sl-1r040j l1: coiltronics ctx20-4 r sense2 : krl sl-1r050j l2: coiltronics ctx33-4 mshdn, shdn1 0v = normal, >2v = shdn ltc1267 ?f010 + 3.3 m f 1n4148 + r1 52.3k 1% r2 100k 1% r1 49.9k 1% r2 150k 1% 100pf LTC1267-ADJ dual regulator with 3.6v/2.5a and 5v/2a outputs typical applicatio n s n u LTC1267-ADJ5 dual regulator with 3.45v/2.5a and 5v/2a outputs 1000pf + + + 1000pf pgate 1 pdrive 1 sense + 1 sense ? 1 sense ? 5 shdn1 pdrive 5 ngate 1 v fb1 pgnd sgnd1 c t1 i th1 i th5 c t5 sgnd5 shdn5 sense + 5 pgate 5 ngate 5 v cc1 v cc v in cap1 cap5 mshdn v cc5 ext v cc LTC1267-ADJ5 c t5 270pf 14 100pf 10 8 9 15 16 20 22 r c5 1k c c1 3300pf c c5 3300pf c t1 270pf r c1 1k 1 3 0.15 m f 0.15 m f 726 27 221 1n4148 28 25 24 18 17 23 19 4 5 13 12 11 6 v out2 5v 2a c out2 220 m f 10v 2 r sense2 0.05 w p-ch si9435dy l2 33 m h d2 mbrs140t3 n-ch si9410dy c in2 100 m f 50v + 3.3 m f 0.1 m f 0.1 m f c in1 100 m f 50v p-ch si9435dy n-ch si9410dy d1 mbrs140t3 c out1 220 m f 10v 2 l1 20 m h r sense1 0.04 w v out1 3.45v 2.5a v in 5.4v to 25v r sense1 : krl sl-1r040j l1: coiltronics ctx20-4 r sense2 : krl sl-1r050j l2: coiltronics ctx33-4 mshdn, shdn1, shdn5 0v = normal, >2v = shdn ltc1267 ?f011 + 3.3 m f 1n4148 + r1 56.2k 1% r2 100k 1% information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
16 ltc1267 LTC1267-ADJ/LTC1267-ADJ 5 g package 28-lead plastic ssop dimensions in inches (millimeters) unless otherwise noted. package descriptio u linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7487 (408) 432-1900 l fax : (408) 434-0507 l telex : 499-3977 ? linear technology corporation 1995 lt/gp 0695 10k ? printed in usa 28ssop 0694 0.301 ?0.311 (7.65 ?7.90) 1234 5 6 7 8 9 10 11 12 14 13 0.397 ?0.407* (10.07 ?10.33) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 0.068 ?0.078 (1.73 ?1.99) 0.002 ?0.008 (0.05 ?0.21) 0.0256 (0.65) bsc 0.010 ?0.015 (0.25 ?0.38) *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.006 inch (0.15mm). 0.005 ?0.009 (0.13 ?0.22) 0 ?8 0.022 ?0.037 (0.55 ?0.95) 0.205 ?0.212* (5.20 ?5.38) part number description comments ltc1142 dual step-down switching regulator controller dual version of ltc1148 ltc1143 dual step-down switching regulator controller dual version of ltc1147 ltc1147 step-down switching regulator controller nonsynchronous, 8-pin, v in 16v ltc1148 step-down switching regulator controller synchronous, v in 20v ltc1149 step-down switching regulator controller synchronous, v in 48v, for standard threshold fets ltc1159 step-down switching regulator controller synchronous, v in 40v, for logic level fets ltc1174 step-down switching regulator with internal 0.5a switch v in 18.5v, comparator/low battery detector ltc1265 step-down switching regulator with internal 1a switch v in 13v, comparator/low battery detector ltc1266 step-up/down switching regulator controller synchronous n- or p-channel fets, comparator/low battery detector ltc1574 step-down switching regulator with internal 0.5a switch v in 18.5v, comparator and schottky diode related parts

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